1. FIELD OF THE INVENTION
The invention relates to the field of generating clock-phases required for sequencing the logic of integrated circuits, and in particular, for metal oxide semiconductor (MOS) circuits.
2. ART BACKGROUND
It is quite common for integrated circuits to provide clock-phases for sequencing the logic in a MOS integrated circuit. These clock-phases are used for sequentially enabling the master and slave stages of edge-triggered flip-flops, which serve as the memory elements in sequential logic. These clock-phases are also used to enable the memory arrays and arithmetic logic units of a computer system. The most common method for providing the clock-phases is to divide the frequency of an external reference clock by two. The external reference clock comprises a series of pulse waveforms. The pulse waveforms are generally rectangular and spaced in equal time intervals. After the division-by-two, the resulting signal has a duty-cycle of 50%, irrespective of the duty-cycle of the external reference clock. Duty-cycle refers to the ratio of the average pulse width to the time period of a pulse wave. The division-by-two method also eliminates any variations in the duty-cycle of the external reference clock. Duty-cycle variation refers to the difference in duty-cycle between idealized waveform of the external reference clock and the actual waveform thereof.
A complication arises if it is required that the frequency of reference clock be the same or even smaller than that of the clock-phase output for the integrated circuit. As such, it is no longer possible to divide the reference clock by two in order to overcome the effects of duty-cycle variations in the external reference clock. It is common to overcome the effects of duty-cycle variations in the reference clock by using a phase-locked loop (PLL) in order to multiply the reference clock by two or some other even number multiple and then to divide the resulting clock-phase by some multiple of 2.
The divide-by-two method of generating clock-phase outputs creates a skew between the reference clock and the clock-phase output. Skew refers to the phase difference between the reference clock and the clock-phase output. While this skew is much less variable than that created by the PLL method, it is, nevertheless, significant. Furthermore, the division-by-two method is limited to a single duty-cycle value of 50%.
To implement a PLL in MOS processes introduces further complications. On the one hand, a PLL is very sensitive to processing parameters and operating conditions. On the other hand, MOS technologies are required to operate over large ranges of processing parameters and operating conditions. The phase difference between the reference clock and the clock-phase outputs is a function of PLL parameters. Thus, in MOS, the phase difference is essentially unpredictable. Nevertheless, the skew is a very critical parameter in the operation of integrated circuits. The greater the skew, the worse become the hold-time requirements of the input signals to the integrated circuit and the longer become the delay-times of output signals from the integrated circuits. The hold-time refers to the minimum length of time during which an input signal or data has to be present and stable in order for it to be sampled correctly by the clock-phases. The delay-time refers to the length of time it takes an output signal to propagate from a flip-flop triggered by the clock-phases to the output port of an integrated circuit. It follows that if the skew cannot be controlled, as in the case with PLL, it is impossible to design integrated circuits to meet hold-time and delay-time specification with the consistency required by mass production thereof.
It is therefore an object of the present invention to generate, without the need of a PLL, clock-phases from a reference clock which has a frequency that is equal to or less than that of the clock-phase output. It is a further object of the present invention to reduce the skew between the reference clock and the clock-phase outputs to a small, well-defined amount, irrespective of the processing parameters, temperature, supply voltage, or load capacitances on the clock-phases.
It is yet another object of the present invention to generate clock-phase outputs with duty-cycles of arbitrary values other than 50%. The duty-cycles may be set to any arbitrary values within the resolution set by a synchronous delay line.
It is yet another object of the present invention to stretch the clock-phases in any clock cycle for any number of clock cycles to facilitate the debugging of integrated circuits. By stretching the clock-phase outputs at selected points in time, critical logic paths in the integrated circuit can be identified. For example, say a particular logic path is suspected to fail at high frequency, and that it is known in which clock periods the path is active. By stretching the clock-phases only in those clock periods in which the suspected path is active, the failure of a particular path can be verified.